In recent years, as semiconductor devices become finer and finer in scale, an LSI constructed having processor elements and a memory integrally mounted on the same chip, the so-called system LSI or particularly embedded DRAM processor, has come to be realized. Further, for increasing processing speed and data bandwidth, a memory-embedded multiprocessor, i.e., a type having a plurality of processors and embedded memory units on one chip, is being proposed for performing parallel processing. The memory-embedded multiprocessors are classified into shared-memory type multiprocessors in which a plurality of processor elements share the access of a memory unit and multiprocessors of a type in which a plurality of processor elements each have its dedicated memory. In a microprocessor of a shared-memory type, in which all combinations of non-overlapping simultaneous access between each processor elements and each partitioned memory sub-units are simultaneously possible, such a system is sometimes used with a crossbar switch array for connections between each of the plurality of processor elements and the memory sub-units.
FIG. 16 is a drawing of prior-art example 1, which schematically shows a manner of connections between processor elements and memory units in a shared-memory type multiprocessor system. In a typical design, there are buses for data, addresses, and control signals, between processor elements and memory units. When the number of buses between a processor and memory units is N, and then if there are N buses provided as shown in FIG. 16, only one processor is allowed to access memory at a time. Which means a bus out of N buses is occupied for communication between the processor and memory. When processor elements simultaneously make requests for memory accesses, all other processors requesting memory access, but one having a current bus accessing privilege, must wait until the communications between this processor element and the memory is over and the bus becomes available. Accordingly, even when memory is divided into small capacity units, simultaneous access is limited to the maximum of available number of buses N. In FIG. 16, note that black circles at bus portions are not permanent bus connections but bus switch arrays and those connections are controlled to set up a bus route from a processor to a target memory.
FIG. 17 is a drawing which explains prior-art example 2. If M sets of N buses (here M<N) are provided as shown in FIG. 17, M processor elements are allowed to communicate with N memory units at the same time. However, since M×N buses are required, the number of buses becomes huge when the number of the processor elements increase. In the drawing, black circles at bus crossing portions are not permanent bus connections but switch arrays. Those switch arrays are controlled to set up a bus route from a processor to a target memory sub-group comprising of one or plural memory units so that the memories are interconnected.
FIG. 18 is a drawing which explains prior-art example 3. In the case of FIG. 18, crossbar areas are provided between processor elements and memory units and, by means of crossbar switches, processor elements and memories are interconnected. The typical crossbar circuit is designed literally to intersect vertical and horizontal lines to form crossbar with bus switch at the intersection point. By providing a path for direct connection between each processor element and each memory unit with the use of a bus switch, the crossbar switch system realizes simultaneous connections of all the combinations of processor elements and memories with smaller hardware size compared to example 2, though it is well known that cross-bar hardware is huge. Although it is not drawn in each figure of example 1, example 2 and example 3 described above, since a plurality of processor elements are not allowed to access the same memory unit at the same time, an arbiter circuit is provided for arbitrating simultaneous requests for accessing the same memory.
In the prior arts discussed above, since the crossbar switch areas must be provided between processor elements and memories as shown in FIG. 18, there is a problem of an increase in the chip space. This problem becomes more serious for large scale integrated system as processor elements and buses are increased in number and, consequently, the system employing the crossbar becomes expensive. If the crossbar switch kind of bus system is not used, it is impossible for a plurality of processor elements to access each target memory unit simultaneously. Therefore, especially for a memory-embedded multiprocessor, though the system performance can be improved by the increase in the bus bandwidth, the cost increases with the increase in the chip area.
In U.S. Pat. No. 5,379,248, a semiconductor memory is disclosed, which makes it possible to provide a more complicated bit line peripheral circuit without increasing the chip size. In this US Patent, ordinary bit lines are laid on a memory cell and other bit lines are laid over the ordinary bit lines so as to intersect the same. Therefore, emphasis is placed on getting more freedom in layout rather than on increasing the bandwidth.
In another patent U.S. Pat. No. 5,943,253, a semiconductor memory is disclosed, which makes it possible to transfer more data without increasing the chip area by providing first data buses and second data buses intersecting each other.
Although the configurations mentioned above include the constituents of the configuration of the present invention partly, they are not such that to attain high speed massive data operation and large bandwidth.